4-bit Counter in Verilog

 

In this blog post, we'll delve into a basic Verilog module that implements a 4-bit counter. This counter increments its value on each clock cycle, and it can be reset to zero. Below, we'll walk through the code step-by-step to understand how it works.

 

The Code

--------------------------------------

module counter(

  input clk,

  input reset,

  output reg[3:0] out

);

 

always @(posedge clk) begin

  if (!reset)

    out <= 0;

  else

    out <= out + 1;

end

 

endmodule

---------------------------------------

• module counter: This line declares a new module named `counter`.
• input clk: This is the clock signal input. The counter will increment on each rising edge of this clock signal.
• input reset: This is the reset signal input. When this signal is low (0), the counter will reset its value to 0.
• output reg[3:0] out: This is a 4-bit wide output register. The `reg` keyword indicates that this is a register that will hold the counter's value.
• always @(posedge clk): This line specifies that the following block of code should be executed on the rising edge (positive edge) of the `clk` signal.
• if (!reset): This condition checks if the `reset` signal is low (0). If `reset` is low, the counter is reset.
• out <= 0: When the reset signal is low, the counter's value (`out`) is set to 0. 
• else: If the `reset` signal is not low (i.e., it is high or 1), the counter increments. 
• out <= out + 1: This increments the counter's value by 1 on each clock cycle.

Waveform:

 How It Works

 

1. Clock Signal: The counter updates its value on the rising edge of the clock signal (`clk`).
2. Reset Signal: When the reset signal (`reset`) is low, the counter is set to 0.
3. Counter Increment: When the reset signal is high, the counter increments its value by 1 on each clock cycle.
4. 4-bit Output: The output (`out`) is a 4-bit register, which means it can represent values from 0 to 15 (in binary: 0000 to 1111).

 

Thank you…